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ipd13n03la g ipf13n03la g IPS13N03LA g ipu13n03la g opti mos ? 2 power-transistor features ? ideal for high-frequency dc/dc converters ? qualified according to jedec 1) for target applications ? n-channel, logic level ? excellent gate charge x r ds(on) product (fom) ? superior thermal resistance ? 175 c operating temperature ? pb-free lead plating; rohs compliant maximum ratings, at t j =25 c, unless otherwise specified parameter symbol conditions unit continuous drain current i d t c =25 c 2) 30 a t c =100 c 30 pulsed drain current i d,pulse t c =25 c 3) 210 avalanche energy, single pulse e as i d =24 a, r gs =25 ? 60 mj reverse diode d v /d t d v /d t i d =30 a, v ds =20 v, d i /d t =200 a/s, t j,max =175 c 6 kv/s gate source voltage 4) v gs 20 v power dissipation p tot t c =25 c 46 w operating and storage temperature t j , t stg -55 ... 175 c iec climatic category; din iec 68-1 55/175/56 value v ds 25 v r ds(on),max 12.8 m ? i d 30 a product summary type ipd13n03la g ipf13n03la g IPS13N03LA g ipu13n03la g package pg-to252-3-11 pg-to252-3-23 pg-to251-3-11 pg-to251-3-21 ordering code q67042-s4269 q67042-s4287 q67042-s4248 q67042-s4270 marking 13n03la 13n03la 13n03la 13n03la rev. 1.71 page 1 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la parameter symbol conditions unit min. typ. max. thermal characteristics thermal resistance, junction - case r thjc - - 3.2 k/w smd version, device on pcb r thja minimal footprint - - 75 6 cm 2 cooling area 5) --50 electrical characteristics, at t j =25 c, unless otherwise specified static characteristics drain-source breakdown voltage v (br)dss v gs =0 v, i d =1 ma 25 - - v gate threshold voltage v gs(th) v ds = v gs , i d =20 a 1.2 1.6 2 zero gate voltage drain current i dss v ds =25 v, v gs =0 v, t j =25 c - 0.1 1 a v ds =25 v, v gs =0 v, t j =125 c - 10 100 gate-source leakage current i gss v gs =20 v, v ds =0 v - 10 100 na drain-source on-state resistance r ds(on) v gs =4.5 v, i d =20 a - 17.5 21.9 m : v gs =10 v, i d =30 a - 10.7 12.8 gate resistance r g - 0.9 - : transconductance g fs | v ds |>2| i d | r ds(on)max , i d =30 a 18 36 - s 5) device on 40 mm x 40 mm x 1.5 mm epoxy pcb fr4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. pcb is vertical in still air. values 2) current is limited by bondwire; with an r thjc =3.2 k/w the chip is able to carry 47 a. 3) see figure 3 4) t j,max =150 c and duty cycle d <0.25 for v gs <-5 v 1) j-std20 and jesd22 rev. 1.71 page 2 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la parameter symbol conditions unit min. typ. max. d y namic characteristics input capacitance c iss - 784 1043 pf output capacitance c oss - 303 402 reverse transfer capacitance c rss -4162 turn-on delay time t d(on) - 5.4 8.0 ns rise time t r - 4.6 6.9 turn-off delay time t d(off) -1523 fall time t f - 2.6 3.9 gate char g e characteristics 6) gate to source charge q gs - 2.7 3.6 nc gate charge at threshold q g(th) - 1.3 1.7 gate to drain charge q gd - 1.8 2.7 switching charge q sw - 3.3 4.7 gate charge total q g - 6.3 8.3 gate plateau voltage v plateau - 3.4 - v gate charge total, sync. fet q g(sync) v ds =0.1 v, v gs =0 to 5 v - 5.5 7.3 nc output charge q oss v dd =15 v, v gs =0 v - 6.6 8.7 reverse diode diode continous forward current i s - - 30 a diode pulse current i s,pulse - - 210 diode forward voltage v sd v gs =0 v, i f =30 a, t j =25 c - 0.95 1.2 v reverse recovery charge q rr v r =15 v, i f = i s , d i f /d t =400 a/s - - 10 nc 6) see figure 16 for gate charge parameter definition t c =25 c values v gs =0 v, v ds =15 v, f =1 mhz v dd =15 v, v gs =10 v, i d =15 a, r g =2.7 : v dd =15 v, i d =15 a, v gs =0 to 5 v rev. 1.71 page 3 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la 1 power dissipation 2 drain current p tot =f( t c ) i d =f( t c ); v gs v ds [v] i d [a] limited by on-state resistance single pulse 0.01 0.02 0.05 0.1 0.2 0.5 10 0 10 -1 10 -2 10 -3 10 -4 10 -5 10 -6 0.01 0.1 1 10 00 000 01 t p [s] z thjc [k/w] 0 10 20 30 40 50 0 50 100 150 200 t c [c] p tot [w] 0 10 20 30 40 0 50 100 150 200 t c [c] i d [a] rev. 1.71 page 4 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la 5 typ. output characteristics 6 typ. drain-source on resistance i d =f( v ds ); t j =25 c r ds(on) =f( i d ); t j =25 c parameter: v gs parameter: v gs 7 typ. transfer characteristics 8 typ. forward transconductance i d =f( v gs ); | v ds |>2| i d | r ds(on)max g fs =f( i d ); t j =25 c parameter: t j 3 v 3.2 v 3.5 v 3.8 v 4.1 v 4.5 v 10 v 0 10 20 30 40 50 0 1020304050 i d [a] r ds(on) [m : ] 25 c 175 c 0 20 40 60 012345 v gs [v] i d [a] 0 10 20 30 40 50 0 102030405060 i d [a] g fs [s] 2.8 v 3 v 3.2 v 3.5 v 3.8 v 4.1 v 4.5 v 10 v 0 10 20 30 40 50 60 0123 v ds [v] i d [a] rev. 1.71 page 5 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la 9 drain-source on-state resistance 10 typ. gate threshold voltage r ds(on) =f( t j ); i d =30 a; v gs =10 v v gs(th) =f( t j ); v gs = v ds parameter: i d 11 typ. capacitances 12 forward characteristics of reverse diode c =f( v ds ); v gs =0 v; f =1 mhz i f =f( v sd ) parameter: t j typ 98 % 0 4 8 12 16 20 24 -60 -20 20 60 100 140 180 t j [c] r ds(on) [m : ] 20 a 200 a 0 0.5 1 1.5 2 2.5 -60 -20 20 60 100 140 180 t j [c] v gs(th) [v] ciss coss crss 10 4 10 3 10 2 10 1 10 100 1000 10000 0102030 v ds [v] c [pf] 25 c 175 c 25 c, 98% 175 c, 98% 1 10 100 1000 0.0 0.5 1.0 1.5 2.0 v sd [v] i f [a] rev. 1.71 page 6 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la 13 avalanche characteristics 14 typ. gate charge i as =f( t av ); r gs =25 : v gs =f( q gate ); i d =25 a pulsed parameter: t j(start) parameter: v dd 15 drain-source breakdown voltage 16 gate charge waveforms v br(dss) =f( t j ); i d =1 ma 5 v 15 v 20 v 0 2 4 6 8 10 12 02468101214 q gate [nc] v gs [v] 20 21 22 23 24 25 26 27 28 29 -60 -20 20 60 100 140 180 t j [c] v br(dss) [v] v gs q gate v gs(th) q g(th) q gs q gd q sw q g 25 c 100 c 150 c 1 10 100 1 10 100 1000 t av [s] i av [a] rev. 1.71 page 7 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la package outline p - to252 - 3 - 11 : o u tli ne footprint: packaging: dimensions in mm rev. 1.71 page 8 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la package outline p - to252 - 3 - 23 : o u tli ne footprint: dimensions in inch [mm] rev. 1.71 page 9 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la package outline p - to251 - 3 - 11 : o u tli ne p-to251-3-21: outline dimensions in inch [mm] rev. 1.71 page 10 2004-07-28
ipd13n03la ipf13n03la IPS13N03LA ipu13n03la published by i n fi neon t ec h no l og i es ag bereich kommunikation st.-martin-stra?e 53 d-81541 mnchen ? infineon technologies ag 1999 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices, please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact your nearest infineon technologies office. infineon technologies' components may only be used in life-support devices or systems with the expressed written approval of infineon technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. rev. 1.71 page 11 2004-07-28

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